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rev. 2.7 7/08 copyright ? 2008 by silicon laboratories si5320-xc3 si5320-xc3 sonet/sdh p recision c lock m ultiplier ic features applications description the si5320 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems including oc-192/oc-48 and 10 gbe. this device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 mhz frequency range and generates a frequency- multiplied clock ou tput that can be configured for operation in the 19, 155, or 622 mhz range. silicon laboratories? dspll ? technology delivers all pll functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters and simplifying design. fec rates are supported with selectable 255/ 238 or 238/255 scaling of the clock multiplication ratios. the si5320 establishes a new standard in performance and integration for ultra-low-jitter clock generation. it operates from a single 3.3 v supply. functional block diagram ? ultra-low-jitter clock output with jitter generation as low as 0.3 ps rms ? no external components (other than a resistor and standard bypassing) ? input clock ranges at 19, 39, 78, 155, 311, and 622 mhz ? digitally-controlled output phase adjust ? output clock ranges at 19, 155, or 622 mhz ? digital hold for lo ss of input clock ? support for forward and reverse fec clock scaling ? selectable loop bandwidth ? loss-of-signal alarm output ? low power ? small size (9x9 mm) ? sonet/sdh line/port cards ? optical modules ? core switches ? digital cross connects ? terabit routers dspll ? frqsel[1:0] clkout+ clkout? 2 cal_actv 2 fec[1:0] bwsel[1:0] 2 biasing & supply regulation rext vsel33 vdd gnd dh_actv signal detect calibration rstn/cal 2 clkin+ clkin? valtime los dblbw 3 phase adjust control mode[2:0] incdelay/tin[2] decdelay/tin[1] fxddelay/tin[0] tout[1:0] infrqsel[2:0] ordering information: see page 36. si5320 si5320
si5320-xc3 2 rev. 2.7
si5320-xc3 rev. 2.7 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schema tic (3.3 v supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1. dspll ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. clock input and output rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3. pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4. digital hold of the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5. hitless reco very from digital hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.6. output phase adjust mo de (pin control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7. output phase adjust mo de (register contro l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8. loss-of-signal alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.9. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10. pll self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11. bias generation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12. differential input ci rcuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13. differential output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15. design and layout guid elines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. pin descriptions: si5320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7. 9x9 mm cbga card lay out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
si5320-xc3 4 rev. 2.7 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min 1 typ max 1 unit ambient temperature t a ?40 2 25 85 c si5320 supply voltage 3 when using 3.3 v supply v dd33 2.97 3.3 3.63 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 2. the si5320 is guaranteed to operate and meet all electrical specifications over an ambi ent temperature of ?40 to 85 c. 3. the si5320 specifications are guarant eed when using the recommended application circuit (including component tolerance) shown in the "2. typical applic ation schematic (3.3 v supply)" on page 17.
si5320-xc3 rev. 2.7 5 figure 1. clkin voltage characteristics figure 2. rise/fall time measurement figure 3. transitionless period on clkin for detecting a los condition note: when using single-ended clock sources, the unused clock input on the si5320 must be ac-coupled to ground. 0.5 v id clkin+ clkin? (clkin+) ? (clkin?) v id b. operation with differential clock input v is a. operation with single-ended clock input clkin+ clkin? note: transmission line termination, when required, must be provided externally. t f t r 80% 20% t los (clkin+) ? (clkin ?) 0 v
si5320-xc3 6 rev. 2.7 figure 4. output phase adjust timing diagrams (pin control) figure 5. output phase adjust timing diagrams (register control) incdelay decdelay t incdec t h t incdec t incdec t h t su t incdec t h t incdec t su t h t su t su sclki sdi load t loadh t setup t hold t sclkh t sclki read sclko sdo 256 sclko periods 01 0 1 start sequence data contents register read envelope t sclko
si5320-xc3 rev. 2.7 7 table 2. dc characteristics, v dd =3.3v (v dd33 = 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current 1 i dd clock in = 622.08 mhz clock out = 19.44 mhz ? 141 155 ma supply current 2 i dd clock in = 19.44 mhz clock out = 622.08 mhz ? 135 145 ma power dissipation using 3.3 v supply clock output p d clock in = 19.44 mhz clock out = 622.08 mhz ? 445 479 mw common mode input voltage 1,2,3 (clkin) v icm 1.0 1.5 2.0 v single-ended input voltage 2,3,4 (clkin) v is see figure 1a 200 ? 500 4 mv pp differential input voltage swing 2,3,4 (clkin) v id see figure 1b 200 ? 500 4 mv pp input impedance (clkin+, clkin?) r in ?80?k differential output voltage swing (clkout) v od 100 load line-to-line 816 906 1100 mv pp output common mode voltage (clkout) v ocm 100 load line-to-line 1.4 1.8 2.2 v output short to gnd (clkout) i sc(?) ?60 ? ? ma output short to v dd25 (clkout) i sc(+) ?15?ma input voltage low (lvttl inputs) v il ??0.8 v input voltage high (lvttl inputs) v ih 2.0 ? ? v input low current (lvttl inputs) i il ??50 a input high current (lvttl inputs) i ih ??50 a internal pulldowns (all lvttl inputs) i pd ??50 a input impedance (lvttl inputs) r in 50 ? ? k output voltage low (lvttl outputs) v ol i o =.5ma ? ? 0.4 v output voltage high (lvttl outputs) v oh i o =.5ma 2.0 ? ? v notes: 1. the si5320 device provides weak 1.5 v internal biasing that enables ac-coupled operation. 2. clock inputs may be driven differentially or single-endedly. w hen driven single-endedly, the unused input should be ac- coupled to ground. 3. transmission line termination, when required, must be provided externally. 4. although the si5320 device can operate with input clock swings as high as 1500 mv pp , silicon laboratories recommends maintaining the input clock amplitude below 500 mv pp for optimal performance.
si5320-xc3 8 rev. 2.7 table 3. ac characteristics (v dd33 = 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit input clock frequency (clkin) fec[1:0] = 00 (non fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin no fec scaling 19.436 38.872 77.744 155.48 310.97 621.95 ? ? ? ? ? ? 21.685 43.369 86.738 173.48 346.95 693.90 mhz input clock frequency (clkin) fec[1:0] = 01 (forward fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 255/238 fec scaling 18.142 36.284 72.568 145.13 290.27 580.54 ? ? ? ? ? ? 20.239 40.478 80.955 161.91 323.82 647.64 mhz input clock frequency (clkin) fec[1:0] = 10 (reverse fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 238/255 fec scaling 20.826 41.652 83.305 166.61 333.22 666.44 ? ? ? ? ? ? 23.234 46.465 92.934 185.87 371.74 743.47 mhz input clock rise time (clkin) t r figure 2 ? ? 11 ns input clock fall time (clkin) t f figure 2 ? ? 11 ns input clock duty cycle c duty_in 40 50 60 % clkout frequency range* frqsel[1:0] = 00 (no output) frqsel[1:0] = 01 frqsel[1:0] = 10 frqsel[1:0] = 11 f o_19 f o_155 f o_622 ? 19.436 155.48 621.95 ? ? ? ? ? 21.685 173.48 693.90 mhz clkout rise time t r figure 2; single-ended; after 3 cm of 50 fr4 stripline ? 213 260 ps clkout fall time t f figure 2; single-ended; after 3 cm of 50 fr4 stripline ? 191 260 ps output clock duty cycle c duty_out differential: (clkout+) ? (clkout?) 48 ? 52 % *note: the si5320 provides a 1/32, 1/16, 1/8, 1/ 4, 1/2, 1, 2, 4, 8, 16, or 32x cloc k frequency multiplication function with an option for additional frequency scaling by a fact or of 255/238 or 238/255 for fec rate compatibility.
si5320-xc3 rev. 2.7 9 rstn/cal pulse width t rstn 20 ? ? ns transitionless period required on clkin for detecting a los condition. infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 t los figure 3 24 / fo_622 16 / fo_622 12 / fo_622 10 / fo_622 9 / fo_622 9 / fo_622 ? ? ? ? ? ? 32 / fo_622 32 / fo_622 32 / fo_622 32 / fo_622 32 / fo_622 32 / fo_622 s recovery time for clearing an los condition valtime = 0 valtime = 1 t val measured from when a valid reference clock is applied until the los flag clears 0.09 12.0 ? ? 0.22 14.1 s incdelay/decdelay pulse width t incdec figure 4 1 ? ? s incdelay/decdelay setup time t su figure 4 1 ? ? s incdelay/decdelay hold time t h figure 4 1 ? ? s register read out read clock high t readh 1?? s register read out serial clock (sclko) frequency 1/t sclko ??4.86mhz register read out clock high to output valid t chov 10 ? ? ns output phase inc/dec serial clock (sclki) frequency 1/t sclki ??1.5mhz output phase inc/dec serial clock (sclki) clock high t sclkh 300 ? ? ns output phase inc/dec serial data (sdi) setup time t setup 300 ? ? ns output phase inc/dec serial data (sdi) hold time t hold 300 ? ? ns output phase inc/dec parallel load (load) clock high t loadh 300 ? ? ns table 3. ac characteristics (continued) (v dd33 = 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit *note: the si5320 provides a 1/32, 1/16, 1/8, 1/ 4, 1/2, 1, 2, 4, 8, 16, or 32x cloc k frequency multiplication function with an option for additional frequency scaling by a fact or of 255/238 or 238/255 for fec rate compatibility.
si5320-xc3 10 rev. 2.7 output phase inc/dec coarse adjust delay increment/ decrement (f o_622 = 622.08 mhz) t cdelay ?2/f 0_622 ?ns output phase inc/dec fine adjust dela y increment/decre- ment t fdelay ?1/ 16 x f 0_622 ?ps table 4. ac characteristics (pll performance characteristics) (v dd33 = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit wander/jitter at 800 hz bandwidth (bwsel[1:0] = 10 and dblbw = 0) jitter tolerance (see figure 8) j tol(pp) f=8hz 1000 ? ?ns f=80hz 100 ? ?ns f=800hz 10 ? ?ns clkout rms jitter generation fec[1:0] = 00 j gen(rms) 12 khz to 20 mhz ? 0.87 1.2 ps 50 khz to 80 mhz ? 0.26 0.35 ps clkout rms jitter generation fec[1:0 = 01, 10 j gen(rms) 12 khz to 20 mhz ? 0.85 1.2 ps 50 khz to 80 mhz ? 0.26 0.35 ps clkout peak-peak jitter generation fec[1:0 = 00 j gen(pp) 12 khz to 20 mhz ? 7.3 10.0 ps 50 khz to 80 mhz ? 3.7 5.0 ps clkout peak-peak jitter generation fec[1:0 = 01, 10 j gen(pp) 12 khz to 20 mhz ? 7.2 10.0 ps 50 khz to 80 mhz ? 3.8 5.0 ps jitter transfer bandwidth (see figure 7) f bw bw = 800 hz ? 800 ? hz wander/jitter transfer peaking j p < 800 hz ? 0.0 0.05 db notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum phase tr ansient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5320 (tpt_mtie) never reaches one nanosecond. table 3. ac characteristics (continued) (v dd33 = 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit *note: the si5320 provides a 1/32, 1/16, 1/8, 1/ 4, 1/2, 1, 2, 4, 8, 16, or 32x cloc k frequency multiplication function with an option for additional frequency scaling by a fact or of 255/238 or 238/255 for fec rate compatibility.
si5320-xc3 rev. 2.7 11 wander/jitter at 1600 hz bandwidth (bwsel[1:0] = 10 and dblbw = 1) jitter tolerance (see figure 8) f = 16 hz 500 ? ? ns f=160hz 50 ? ? ns f = 1600 hz 5 ? ? ns clkout rms jitter generation fec[1:0] = 00 j gen(rms) 12 khz to 20 mhz ? 0.78 1.2 ps 50 khz to 80 mhz ? 0.25 0.35 ps clkout peak-peak jitter generation fec[1:0] = 00 j gen(pp) 12 khz to 20 mhz ? 7.0 9.0 ps 50 khz to 80 mhz ? 3.8 5.0 ps jitter transfer bandwidth (see figure 7) f bw bw = 1600 hz ? 1600 ? hz wander/jitter transfer peaking j p < 1600 hz ? 0.00 0.05 db wander/jitter at 1600 hz bandwidth (bwsel[1:0] = 01 and dblbw = 0) jitter tolerance (see figure 8) j tol(pp) f = 16 hz 1000 ? ? ns f = 160 hz 100 ? ? ns f = 1600 hz 10 ? ? ns clkout rms jitter generation fec[1:0] = 00 j gen(rms) 12 khz to 20 mhz ? 0.82 1.0 ps 50 khz to 80 mhz ? 0.26 0.35 ps clkout rms jitter generation fec[1:0] = 01, 10 j gen(rms) 12 khz to 20 mhz ? 0.79 1.0 ps 50 khz to 80 mhz ? 0.26 0.35 ps clkout peak-peak jitter generation fec[1:0] = 00 j gen(pp) 12 khz to 20 mhz ? 7.3 10.0 ps 50 khz to 80 mhz ? 3.8 5.0 ps clkout peak-peak jitter generation fec[1:0] = 01, 10 j gen(pp) 12 khz to 20 mhz ? 7.1 10.0 ps 50 khz to 80 mhz ? 4.3 5.0 ps jitter transfer bandwidth (see figure 11) f bw bw = 1600 hz ? 1600 ? hz wander/jitter transfer peaking j p < 1600 hz ? 0.0 0.1 db table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum phase tr ansient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5320 (tpt_mtie) never reaches one nanosecond.
si5320-xc3 12 rev. 2.7 wander/jitter at 3200 hz bandwidth (bwsel[1:0] = 01 and dblbw = 1) jitter tolerance (see figure 8) f = 32 hz 500 ? ? ns f = 320 hz 50 ? ? ns f = 3200 hz 5 ? ? ns clkout rms jitter generation fec[1:0] = 00 j gen(rms) 12 khz to 20 mhz ? 0.72 0.9 ps 50 khz to 80 mhz ? 0.24 0.3 ps clkout peak-peak jitter generation fec[1:0] = 00 j gen(pp) 12 khz to 20 mhz ? 6.8 10.0 ps 50 khz to 80 mhz ? 3.7 5.0 ps jitter transfer bandwidth (see figure 7) f bw bw = 3200 hz ? 3200 ? hz wander/jitter transfer peaking j p < 3200 hz ? 0.05 0.1 db wander/jitter at 3200 hz bandwidth (bwsel[1:0] = 00 and dblbw = 0) jitter tolerance (see figure 8) j tol(pp) f=32hz 1000 ? ?ns f=320hz 100 ? ?ns f = 3200 hz 10 ? ?ns clkout rms jitter generation fec[1:0] = 00 j gen(rms) 12 khz to 20 mhz ? 0.86 1.2 ps 50 khz to 80 mhz ? 0.29 0.4 ps clkout rms jitter generation fec[1:0] = 01, 10 j gen(rms) 12 khz to 20 mhz ? 0.79 1.2 ps 50 khz to 80 mhz ? 0.28 0.4 ps clkout peak-peak jitter generation fec[1:0] = 00 j gen(pp) 12 khz to 20 mhz ? 7.7 10.0 ps 50 khz to 80 mhz ? 3.9 5.0 ps clkout peak-peak jitter generation fec[1:0] = 01, 10 j gen(pp) 12 khz to 20 mhz ? 7.2 10.0 ps 50 khz to 80 mhz ? 4.0 5.0 ps jitter transfer bandwidth (see figure 7) f bw bw = 3200 hz ? 3200 ?hz wander/jitter transfer peaking j p < 3200 hz ? 0.05 0.1 db table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum phase tr ansient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5320 (tpt_mtie) never reaches one nanosecond.
si5320-xc3 rev. 2.7 13 wander/jitter at 6400 hz bandwidth (bwsel[1:0] = 00 and dblbw = 1) jitter tolerance (see figure 8) f = 64 hz 500 ? ? ns f=640hz 50 ? ? ns f = 6400 hz 5 ? ? ns clkout rms jitter generation fec[1:0] = 00 j gen(rms) 12 khz to 20 mhz ? 0.7 1.0 ps 50 khz to 80 mhz ? 0.25 0.3 ps clkout peak-peak jitter generation fec[1:0] = 00 j gen(pp) 12 khz to 20 mhz ? 6.6 9.0 ps 50 khz to 80 mhz ? 3.8 5.0 ps jitter transfer bandwidth (see figure 7) f bw bw = 6400 hz ? 6400 ? hz wander/jitter transfer peaking j p < 6400 hz ? 0.05 0.1 db wander/jitter at 6400 hz bandwidth (bwsel[1:0] = 11 and dblbw = 0) jitter tolerance (see figure 8) (1/1 scaling) j tol(pp) f=64hz 1000 ? ?ns f=640hz 100 ? ?ns f = 6400 hz 10 ? ?ns clkout rms jitter generation fec[1:0] = 00 (1/1 scaling) j gen(rms) 12 khz to 20 mhz ? 1.0 1.4 ps 50 khz to 80 mhz ? 0.38 0.5 ps clkout rms jitter generation fec[1:0] = 01, 10 (255/238, 238/255 scaling) j gen(rms) 12 khz to 20 mhz ? 0.94 1.4 ps 50 khz to 80 mhz ? 0.41 0.6 ps clkout peak-peak jitter generation fec[1:0] = 00 (1/1 scaling) j gen(pp) 12 khz to 20 mhz ? 9.4 12.0 ps 50 khz to 80 mhz ? 4.7 5.5 ps clkout peak-peak jitter generation fec[1:0] = 01, 10 (255/238, 238/255 scaling) j gen(pp) 12 khz to 20 mhz ? 8.3 12.0 ps 50 khz to 80 mhz ? 4.6 5.5 ps jitter transfer bandwidth (see figure 7) f bw bw = 6400 hz ? 6400 ?hz wander/jitter transfer peaking j p < 6400 hz ? 0.05 0.1 db table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum phase tr ansient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5320 (tpt_mtie) never reaches one nanosecond.
si5320-xc3 14 rev. 2.7 wander/jitter at 12800 hz bandwidth (bwsel[1:0] = 11 and dblbw = 1) jitter tolerance (see figure 8) f = 128 hz 500 ? ? ns f = 1280 hz 50 ? ? ns f = 12800 hz 5 ? ? ns clkout rms jitter generation fec[1:0] = 00 (1/1 scaling) j gen(rms) 12 khz to 20 mhz ? 0.74 1.0 ps 50 khz to 80 mhz ? 0.30 0.4 ps clkout peak-peak jitter generation fec[1:0] = 00 (1/1 scaling) j gen(pp) 12 khz to 20 mhz ? 6.9 9.0 ps 50 khz to 80 mhz ? 4.0 5.0 ps jitter transfer bandwidth (see figure 7) f bw bw = 12,800 hz ? 12800 ? hz wander/jitter transfer peaking j p < 12,800 hz ? 0.05 0.1 db acquisition time t aq rstn/cal high to cal_actv low, with valid clock input and valtime = 0 ? 300 350 ms clock output wander with temperature gradient 1,2 c co_tg stable input clock; temperature gradient <10 c/min; 800 hz loop bw ? ? 50 ps/ c/ min initial frequency accuracy in digital hold mode (first 100 ms with supply voltage and tem- perature held constant) c dh_fa stable input clock selected until entering digital hold ? ? 10 ppm clock output frequency accuracy over temperature in digital hold mode c dh_t constant supply voltage ? 16.7 40 ppm / c clock output frequency accuracy over supply voltage in digital hold mode c dh_v33 constant temperature ? ? 250 ppm /v table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum phase tr ansient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5320 (tpt_mtie) never reaches one nanosecond.
si5320-xc3 rev. 2.7 15 clock output phase step 3 (see figure 9) t pt_mtie when hitlessly recovering from digital hold mode 1/1 ? ?200 0 200 ps clock output phase step slope 3 (see figure 9) bwsel[1:0] = 11, fec[1:0] = 00, dblbw = 0 bwsel[1:0] = 00, fec[1:0] = 00, dblbw = 0 bwsel[1:0] = 01, fec[1:0] = 00, dblbw = 0 bwsel[1:0] = 10, fec[1:0] = 00, dblbw = 0 m pt when hitlessly recovering from digital hold mode 6400 hz, no scaling 3200 hz, no scaling 1600 hz, no scaling 800 hz, no scaling ? ? ? ? ? ? ? ? 10 5 2.5 1.25 ps/ s table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 = 3.3 v 10%, ta = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum phase tr ansient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5320 (tpt_mtie) never reaches one nanosecond.
si5320-xc3 16 rev. 2.7 figure 6. typical si5320 phase noise (clkin = 155.52 mhz, clkout = 622.08 mhz, and loop bw = 800 hz) table 5. absolute maximum ratings parameter symbol value unit 3.3 v dc supply voltage v dd33 ?0.5 to 3.7 v lvttl input voltage v dig ?0.3 to (v dd33 + 0.3) v maximum current any output pin 50 ma operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k )1.0kv note: permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the ope rational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ja still air 46 c/w 10 1 -160 -140 -120 -100 -80 -60 -40 -20 0 10 6 10 5 10 4 10 3 10 2 10 7 10 8 offset frequency phase noise (dbc/hz)
si5320-xc3 rev. 2.7 17 2. typical application schematic (3.3 v supply) 10 k 1% los clkin+ mode[2:0] clkin- input clock source loss of signal (los) digital hold active los validation time dh_actv rstn/cal fec[1:0] bwsel[1:0] pll bandwidth select fec scaling select (14/15, 15/14) reset/calibration control cal_actv frqsel[1:0] clkout+ clkout? clock output (19, 155, or 622 mhz) clock output frequency select calibration active status output rext vsel33 vdd25 vdd33 gnd 0.1 f 3.3 v supply 2200 pf 22 pf si5320 infrqsel[2:0] input clock frequency select (19, 38, 77, 155, 311, or 622 mhz) 33 f dblbw bandwidth doubling ferrite bead 0.1 f 0.1 f 100 0.1 f 0.1 f serial clock output phase increment/read register/load phase offset serial data output mode select tout[1] tout[0] phase decrement/serial data input fixed delay mode control/serial clock input incdelay/tin[2} decdelay/tin[1] fxddelay/tin[0] valtime
si5320-xc3 18 rev. 2.7 3. functional description the si5320 is a high-performance precision clock multiplication and clock generation device. this device accepts a clock input in the 19, 38, 77, 155, 311, or 622 mhz range, attenuates si gnificant amounts of jitter, and multiplies the input clock frequency to generate a clock output in the 19, 155, or 622 mhz range. additional optional scaling by a factor of either 255/238 (15/14) or 238/255 (14/15) is provided for compatibility with systems that provide or require clocks that are scaled for forward error correction (fec) rates. typical applications for the si532 0 in sonet/sdh systems would be the generation an d/or cleaning of 19.44, 155.52, or 622.08 mhz clocks from 19.44, 38.88, 77.76, 155.52, 311.04, or 622.08 mhz clock sources. the si5320 employs silicon laboratories dspll ? technology to provide excellent jitter performance while minimizing the external component count and maximizing flexibility and ea se-of-use. the si5320?s dspll phase locks to the input clock signal, attenuates jitter, and multiplies the clock frequency to generate the device?s sonet/sdh-compliant clock output. the dspll loop bandwidth is user-selectable, allowing the si5320?s jitter performance to be optimized for different applications. the si5320 can produce a clock output with jitter generation as low as 0.3 ps rms (see table 4), making the device an ideal solution for clock multiplication in sonet/sdh (including oc-48 and oc- 192) and gigabit ethernet systems. the si5320 monitors the clock input signal for loss-of- signal, and provides a loss-of-signal (los) alarm when missing pulses are detected. the si5320 provides a digital hold capability to co ntinue generation of a stable output clock when the input reference is lost. 3.1. dspll ? the si5320?s phase-locked loop (pll) uses silicon laboratories' dspll technology to eliminate jitter, noise, and the need for external loop filter components found in traditional pll implementations. this is achieved by using a digital signal processing (dsp) algorithm to replace the loop filter commonly found in analog pll designs. this algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage- controlled oscillator (vco). the technology produces clocks with less jitter than is generated using traditional methods. see figure 6 for an example phase noise plot. in addition, because external loop filter components are not required, sensitive noise entry points are eliminated, making the dspll less susceptible to board-level noise sources. this digital technology also allows for highly-stable and consistent operation over a ll process, temperature, and voltage variations. the benefits are smaller, lower power, cleaner, more reliable, and easier-to-use clock circuits. 3.1.1. selectable loop filter bandwidth the digital nature of the dspl l loop filter allows control of the loop filter parameters without the need to change external components. the si5320 provides the user with up to eight user-selectable loop bandwidth settings for different system requirements. the base loop bandwidth is selected using the bwsel [1:0] along with dblbw = 0 pins. when dblbw is driven high, the bandwidth selected on the bwsel[1:0] pins is doubled. (see table 7.) when dblbw is asserted, the si5320 shows improved jitter generation performance. dblbw function is defined only when hitless recovery and fec scaling are disabled. therefore, when dblbw is high, the user must also drive fxddelay high and fec[1:0] to 00 for proper operation. 3.2. clock input and output rate selection the si5320 provides a 1/32x , 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for fec rate compatibility. output rates va ry in accordance with the input clock rate. the multiplic ation factor is configured by selecting the input and output clock frequency ranges for the device. the si5320 accepts an input clock in the 19, 38, 77, 155, 311, or 622 mhz frequency range. the input frequency range is selected using the infrqsel[2:0] pins. the infrqsel[2:0] settings and associated output clock rates are given in table 8. the si5320?s dspll phase locks to the clock input signal to generate an internal vco frequency that is a multiple of the input clock frequency. the internal vco frequency is divided down to produce a clock output in the 19, 155, or 622 mhz frequency range. the clock output range is selected using the frequency select (frqsel[1:0]) pins. the frqsel[1:0] settings and associated output clock ra tes are given in table 9. the si5320 clock input frequencies are variable within the range specified in table 3 on page 8. the output rates scale accordingly. wh en a 19.44 mhz input clock is used with no fec scaling enabled, the clock output frequency is 19.44, 155.52, or 622.08 mhz.
si5320-xc3 rev. 2.7 19 3.2.1. fec rate conversion the si5320 provides a 1/32x , 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for fec rate compatibility. the multiplicatio n factor is configured by selecting the input and output clock frequency ranges for the device. the additio nal frequency scaling by a factor of either 255/238 or 238/255 for fe c compatibility is selected using the fec[1:0] control inputs. (see table 10.) for example, a 622.08 mhz output clock (a non-fec rate) can be generated from a 19.44 mhz input clock (a non-fec rate) by setting infrqsel[2:0] = 001 (19.44 mhz range), setting frqsel [1:0] = 11 (32x multiplication), and setting fec[1:0] = 00 (no fec scaling). a 666.51 mhz output clock (a fec rate) can be generated from a 19.44 mhz input clock (a non-fec rate) by setting infrqsel[2:0] = 001 (19.44 mhz range), setting frqsel [1:0] = 11 (32x multiplication), and setting fec[1:0] = 01 (255/238 fec scaling). finally, a 622.08 mhz output clock (a non-fec rate) can be generated from a 20.83 mhz input clock (a fec rate) by setting infrqsel[2:0] = 001 (19.44 mhz range), setting frqsel [1:0] = 11 (32x multiplication), and setting fec[1:0] = 10 (238/255 fec scaling). 3.3. pll performance the si5320 pll is designed to provide extremely low jitter generation, high jitter tolerance, and a well- controlled jitter transfer function with low peaking and a high degree of jitter attenuation. 3.3.1. jitter generation jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. generated jitter arises from sources within the vco and other pll components. jitter generation is also a function of the pll bandwidth setting. higher loop bandwidth settings ma y result in lower jitter generation, but may also result in less attenuation of jitter on the input clock signal. 3.3.2. jitter transfer jitter transfer is defined as th e ratio of output signal jitter to input signal jitter for a specified jitter frequency. the jitter transfer characteristic determines the amount of input clock jitter th at passes to the outputs. the dspll technology used in the si5320 provides tightly- controlled jitter transfer curves because the pll gain parameters are determined by digital circuits that do not vary over supply voltage, process, and temperature. in a system application, a we ll-controlled transfer curve table 7. loop bandwidth settings loop bandwidth bwsel1 bwsel0 dblbw * 12800 hz 1 1 1 6400 hz 1 1 0 6400 hz 0 0 1 3200 hz 0 0 0 3200 hz 0 1 1 1600 hz 0 1 0 1600 hz 1 0 1 800 hz 1 0 0 *note: when dblbw = 1, fxddelay must be asserted and fec scaling must be disabled. table 8. nominal clock input frequencies input clock frequency range infrqsel2 infrqsel1 infrqsel0 reserved111 622mhz110 311mhz101 155mhz 100 77mhz 011 38mhz 010 19mhz 001 reserved000 table 9. nominal clock output frequencies output clock frequency range frqsel1 frqsel0 622 mhz 1 1 155 mhz 1 0 19 mhz 0 1 driver powerdown 0 0 table 10. fec frequency scalings fec frequency scaling fec1 fec0 1/1 0 0 255/238 0 1 238/255 1 0 reserved 1 1
si5320-xc3 20 rev. 2.7 minimizes the output clock jitter variation from board to board, providing more consistent system level jitter performance. the jitter transfer characteristic is a function of the bwsel[1:0] setting. (see table 7.) lower bandwidth selection settings result in mo re jitter attenuation of the incoming clock but may result in higher jitter generation. table 4 on page 10 gives the 3 db bandwidth and peaking values for specified bwsel settings. figure 7 shows the jitter tran sfer curve mask. figure 7. pll jitter transfer mask/template 3.3.3. jitter tolerance jitter tolerance for the si5320 is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock. the tolerance is a function of the jitter frequency, because tolerance improves for lower input jitter frequency. see figure 8. figure 8. jitter tolerance mask/template 3.4. digital hold of the pll when no valid input clock is available, the si5320 digitally holds the internal os cillator to its last frequency value. this provides a stable clock to the system until an input clock is again valid. this clock maintains very stable operation in the presence of constant voltage and temperature. the frequency accuracy specifications for digital hold mode are given in table 4 on page 10. 3.5. hitless recove ry from digital hold when the si5320 device is locked to a valid input clock, a loss of the input clock causes the device to automatically switch to di gital hold mode. when the input clock signal returns, the device performs a ?hitless? transition from digital hold mode back to the selected input clock. that is, the device performs ?phase build-out? to absorb the phase difference between the internal vco clock operating in digital hold mode and the new/returned input clock. the maximum phase step size seen at the clock output during this transition and the maximum slope for this phase step are given in table 4 on page 10. this feature can be disabled by asserting the fxddelay pin. when the fxddelay pin is high, the output clock is phase and frequency locked with a known phase relationship to the input clock. consequently, any abrupt phase change on the input clock propagates through the device, and the output slews at the selected loop bandwidth until the original phase relationship is restored. note: when the dblbw is asserted, hitless recovery must also be disabled by driving fxddelay high for proper operation. when the device is in output phase adjust mode, the state of fxddelay cannot be changed. upon entry into phase adjust mode, t he device remembers the last valid state of fxddelay, and this setting is fixed while the device is in output phase adjust mode. figure 9. recovery from digital hold 3.6. output phase adjust mode (pin control) the incdelay and decdelay pins adjust the phase of the si5320 clock output. adjustment is accomplished by driving a pulse (a transition from low to high and then back to low) into one of th ese pins as the other pin is jitter transfer 0 db f bw f jitter peaking ?20 db/dec. jitter out jitter in (s) input jitter amplitude 10 ns f bw ?20 db/dec. f jitter in excessive input jitter range recovery from digital hold m pt t pt_mtie
si5320-xc3 rev. 2.7 21 held at a logic low level. each pulse on the incdelay pin adds a fixed delay to the si5320 clock output. the amount of delay time is equal to twice the period of a 622 mhz output clock (t delay =2/f o_622 ). each pulse on the decdelay pin removes a fixed amount of delay from the si5320 clock output. the fixed delay time is equal to twice the period of the 622 mhz output clock (t delay =2/f o_622 ). the frequency of the 622 mhz output clock (f o_622 ) is nominally 32x the frequency of the input clock. the frequency of the 622 mhz output clock (f o_622 ) is scaled according to the setting of the fec[1:0] pins. when the phase of the si53 20 clock output is adjusted using the incdelay and/or decdelay pins, the output clock will typically begin to move within 2 s. however, it will move to it s new phase setting at a rate of change that is determined by the setting of the bwsel[1:0] pins. note: incdelay and decdelay are ignored when the si5320 operates in digital hold (dh) mode. 3.7. output phase adjust mode (register control) the si5320 can be placed in a special mode to externally adjust the devic e output clock phase. this mode of operation can be used to manually increment or decrement the output clock phase using internal device registers. the si5320 has two output phase adjust options: coarse phase adjust and fine phase adjust. coarse phase adjust allows the clock output phase to be incremented or decremented in 3.22 ns steps, based on an output clock frequency of 622.08 mhz (step size = 2/ f clkout ), by forcing the pll feedback divider circuitry to spit or swallow clock cycles. fine phase adjust is done by externally setting the valu e of the offset dac in the phase detector. fine phase adjust allows the clock output phase to be incremented or decremented in 100 ps steps, based on an output clock frequency of 622.08 mhz (step size = 1/(16 x f clkout )). coarse phase adjust and fine phase adjust can be used together or separately. in this mode of operation, the state of fxddelay cannot be changed. instead, the device remembers the last valid state of fxddelay and uses this setting for the entire time the device is in output phase adjust mode. for example, if fxddelay is tied low when the device enters output phase adjust mode, hitless recovery from digital hold is enabled during output phase adjust mode. if fxddelay is tied high when the device enters output phase adjust mode, hitless recovery from digital hold is disabled during output phase adjust mode. in either case, the output phase can be adjusted. in the fine phase adjust mode, it takes two steps to manually adjust the device output clock phase. the first step, register read out, is used to acquire the current phase detector value. the second step, output phase increment/decrement, is used to manually increment or decrement the dac value, and write it back to the si5320 to achieve the desired phase adjust. the mode [2:0] pins determine whether the device is being used to read the phase detector dac value or increment/ decrement the output phase. table 11 lists the device control pins and associated functions when the device is in output phase adjust mode. table 11. output phase adjust control pins device pin i/o location normal operation register read out output phase inc/dec mode[2] i b6 0 1 0 mode[1] i b7 0 1 0 mode[0] i c8 0 0 1 incdelay/t in [2] i b2 incdelay read load decdelay/t in [1] i b3 decdelay n/a sdi fxddelay/t in [0] i b4 fxddelay envsel sclki t out [1] o a5 0 sdo n/a t out [0] o a6 0 sclko n/a
si5320-xc3 22 rev. 2.7 3.7.1. register read out to read the phase detector dac value, the mode [2:0] pins must be set to 110. when configured to read this register value, the device operates normally except that a high level on the read input signal causes the values of many of the internal digital registers to be period ically copied into parallel shadow registers. after a brief delay, the values in the shadow registers are serially shifted out through the serial data output pin, sdo, and synchronized to the serial clock output, sclko. the register read envelope is bounded by a four-bit preamble 0101. as long as read remains high, the internal registers are re- sampled and shifted out once every 256 cycles of sclko. the complete i/o da ta format and timing for register readout is shown in figure 5 on page 6. during register read out, the sclko and sdo pins drive out a low value exc ept when driving out the register read envelope. once a readout sequence commences, the entire register read envelope is shifted out, regardless of any changes on read. the envsel signal should be set high to read the phase detector dac value. the 119-bit read register chain is defined as follows: the data contents of the register read envelope are shifted out from left to right. 3.7.2. output phase increment/decrement mode [2:0] pins are set to 001 to write back the desired dac codes. serial clock and data inputs (sclki and sdi) are used to serially program a 27-bit chain of phase adjust registers. a parallel load signal (load) is then used to drive the serially-programmed values into the phase offset (auto-zeroing) dac and into the pulse spitting/swallowing circuitry. th is allows external control of the phase offset dac for fine output phase adjust and external control of the pulse spitting/swallowing circuitry for coarse phase adjust of the si5320 output phase. timing constraints for programming the si5320 phase adjust registers and for loading in the new values are shown in figure 5 on page 6. the 27-bit phase adjust register chain is defined as follows: the register bits pddac[6:0] provide output phase increments as small as 100 ps. the spit and swallow register bits provide coarse control of the si5320 output phase, nominally 3.22 ns for a 622.08 mhz output clock. this register chain is filled from left to right. the first bit to be serially shifted in is pddac[6], then pddac[5], then pddac[4], etc. a rising edge on sclki is required to program each bit into the output phase adjust register. it takes 27 rising edges of sclki to fully program the phase adjust register chain. the last 18 bits in the output phase adju st register are reserved by the si5320 and must be set to 1000000_1_1_1000000_1_1. a rising edge on the load signal will load the programmed values directly into the phase offset (auto- zeroing) dac. if eith er the spit or swallow register bits are programmed high, a rising edge on load will cause the associated circuitry to spit or swallow a single 311 mhz (3.22 ns) pulse. to spit or swallow several pulses in a row, apply several consecutive pulses of load. if both the spit and swallow register bits are programmed high, neither spit nor swallow functions will be performed. table 12 shows the valid settings for the spit and swallow bits. the si5320-xc3 has a special production test mode. this mode is entered when the mode select lines are set to mode[2:0] = 111. if this happens during operation, the part is not guaranteed to meet data sheet specifications. furthermore, because no application can guarantee that the state of all three mode select lines will switch simultaneously, th e mode select lines should be changed one bit at a ti me. this process will ensure that the device never enters the state mode[2:0]=111. because the si5320 samples the state of the mode select lines approximately every 210 ns, a delay of approximately 500 ns between states is recommended to ensure the device samples each state correctly. an example of how this might be done is as follows: to change from normal operation to the register read mode, the following sequence should be used: mode[2:0] = 000, 100, 110. to change from register read to the register write mode, use this sequence: mode[2:0 ] = 110, 100, 000, 001. while it is unlikely for any problems caused by this timing to occur, it is possib le to inadvertently enter the mode 111 unless this procedure is followed. reserved[21:0] pddac[6 :0] reserved[89:0] pddac[6:0] spit swallow reserved[17:0] table 12. spit and swallow register bit configuration (f o_622 = 622 mhz) spit swallow outcome 0 0 no phase adjust occurs 1 0 3.22 ns phase decrement 0 1 3.22 ns phase increment 1 1 no phase adjust occurs
si5320-xc3 rev. 2.7 23 the following steps illustrate a hypothetical output phase decrement sequence: 1. read the current device phase detector dac values by setting mode[2:0] to 110, setting envsel high for the duration of the register read cycle, and pulsing read high. following the 4-bit preamble 0101, the device will return the contents of the 119- bit read register. the following example assumes the phase detector dac value is 1000000. a read of the read register would return: 1000000_xxxx_1000000_xxxx_1000000_xxx... 2. perform a coarse phase decrement on the device clock outputs. set mode[2:0] to 001 and use the serial clock input (sclki) and serial data input (sdi) to load the following values into the phase adjust register chain: 1000000_1_0_1000000_0_0_1000000_0_0 note: the reserved[17:0] bits must always be set to 1000000_0_0_1000000_0_0 during output phase adjust mode. this exampl e assumes the previous value of the phase detector dac is 1000000. apply a single pulse to the parallel load pin (load). this will cause the si5320 phase detector to remove a fixed delay from the device clock outputs. the amount of delay removed from the clock outputs is equal to twice the period of a 622 mhz nominal clock (t delay = 2/f o_622 ), or 3.22 ns. 3. read the current device phase detector dac values by setting mode[2:0] to 110, setting envsel high for the duration of the register read cycle, and pulsing read high. following the 4-bit preamble 0101, the device will return the contents of the 119- bit read register. the following example assumes the phase detector dac value is 1000000. a read of the read register would return: 1000000_xxxx_1000000_xxxx_1000000_xxx... 4. perform a fine phase decrement on the device clock outputs. set mode[2:0] to 001 and use the serial clock input (sclki) and serial data input (sdi) to load the following values into the phase adjust register chain: 1000001_0_0_1000000_0_0_1000000_0_0 apply a single pulse to the parallel load pin (load). this will cause the si5320 ph ase detector to remove a fixed amount of delay from the device clock outputs. the amount of delay removed from the clock outputs is equal to 1/16th the period of a 622 mhz nominal clock (t delay =1/(16xf o_622 )), or 100 ps . the following steps illustrate a hypothetical output phase increment sequence: 1. read the current device phase detector dac values by setting mode[2:0] to 110, setting envsel high for the duration of the register read cycle, and pulsing read high. following the 4-bit preamble 0101, the device will return the contents of the 119- bit read register. the following example assumes the phase detector dac value is 1000000. a read of the read register would return: 1000000_xxxx_1000000_xxxx_1000000_xxx... 2. perform a coarse phase increment on the device clock outputs. set mode[2:0] to 001 and use the serial clock input (sclki) and serial data input (sdi) to load the following values into the phase adjust register chain: 1000000_0_1_1000000_0_0_1000000_0_0 apply a single pulse to the parallel load pin (load). this will cause the si5320 ph ase detector to add a fixed amount of delay to the device clock outputs. the amount of delay added to the clock outputs is equal to twice the period of a 622 mhz nominal clock (t delay = 2/f o_622 ), or 3.22 ns. 3. read the current device phase detector dac values by setting mode[2:0] to 110, setting envsel high for the duration of the register read cycle, and pulsing read high. following the 4-bit preamble 0101, the device will return the contents of the 119- bit read register. the following example assumes the phase detector dac value is 1000000. a read of the read register would return: 1000000_xxxx_1000000_xxxx_1000000_xxx... 4. perform a fine phase increm ent on the device clock outputs. set mode[2:0] to 001 and use the serial clock input (sclki) and serial data input (sdi) to load the following values into the phase adjust register chain: 0111111_0_0_1000000_0_0_1000000_0_0 apply a single pulse to the parallel load pin (load). this will cause the si5320 phase detector to add a fixed delay to the device clock outputs. the amount of delay added to the clock outputs is equal to 1/16th the period of a 622 mhz nominal clock (t delay =1/(16xf o_622 )), or 100 ps. for a coarse phase increment or decrement, the amount of delay time added or subtracted to the clock output is equal to twice the period of a nominal 622.08 mhz output clock, or 3.22 ns (2xt 622.08 = 3.22 ns). for a fine phase increment or decrement, the amount of delay time added or subtracted to the clock output is equal to 1/16th the period of a nominal 622 mhz output clock or 100 ps (1/ 16 x t 622.08 = 100 ps). the frequency of f o_622 is scaled according to the setting of the fec[1:0] pins. when the phase of the si5320 clock output is adjusted using the output phase adju st mode, the output clock
si5320-xc3 24 rev. 2.7 will typically begin to move within 2 s. however, it will move to its new phase setting at a rate of change that is determined by the settin g of the bwsel[1:0] pins. 3.8. loss-of-signal alarm the si5320 has loss-of-sig nal (los) circuitry that constantly monitors the clkin input clock for missing pulses. the los circuitry sets a los output alarm signal when missing pulses are detected. the los circuitry operates as follows. regardless of the selected input clock frequency range, the los circuitry divides down the input clock into the 19 mhz range. the los circuitry then over-samples this divided-down input clock to search for extended periods of time without input clock transitions. if the los circuitry detects four consecutive samples of the divided-down input clock that are the same state (i.e., 1111 or 0000), a los conditi on is declared, the si5320 goes into digital hold mode, and the los output alarm signal is set high. the los sampling circuitry runs at a frequency of f o_622/8 , where f o_622 is the output clock frequency when the frqsel[1:0] pins are set to 11. table 3 on page 8 lists the minimum and maximum transitionless time periods required for declaring a los on the input clock (t los ). once the los alarm is asserted, it is held high until the input clock is validated over a time period designated by the valtime pin. when valtime is low, the validation time period is about 100 ms. when valtime is high, the validation time period is about 13 s. if another los condition is detected on the input clock during the validation time (i.e., if another set of 1111 or 0000 samples are detected), the los alarm remains asserted, and the validation time starts over. when the los alarm is finally released, the si5320 exits digital hold mode and locks to the input clock. the los alarm is automatically set high at power-on and at every low- to-high transition of the rstn/cal pin. in these cases, the si5320 undergoes a self-calibration before releasing the los alarm and locking to the input clock. the si5320 also provides an output indicating the digital hold status of the device, dh_actv. the si5320 only enters the digital hold mode upon the loss of the input clock. when this occurs, the los alarm will also be active. therefore, applications that require monitoring of the status of the si5320 need only monitor the cal_actv and either the los or dh_actv outputs to know the state of the device. 3.9. reset the si5320 provides a reset/calibration pin, rstn/ cal, which resets the device and disables the outputs. when the rstn/cal pin is driven low, the internal circuitry enters into the reset mode, and all lvttl outputs are forced into a high-impedance state. also, the clkout+ and clkout? pins are forced to a nominal cml logic low and high respectively (see figure 10). this feature is useful for in-circuit test applications. a low-to-high transition on rstn/cal initializes all digital logic to a known condition and initiates self-calibration of the dspll. upon completion of self-calibration, the dspll begins to lock to the clock input signal. figure 10. clkout equivalent circuit, rstn/cal asserted low 3.10. pll self-calibration the si5320 achieves optimal jitter performance by using self-calibration circuitry to set the vco center frequency and loop gain parameters within the dspll. internal circuitry generates self calibration automatically on powerup or after a loss of power condition. self- calibration can also be manu ally initiated by a low-to- high transition on the rstn/cal input. a self-calibration sh ould be initiated after changing the state of the fec[1:0] inputs. whether manually initiated or automatically initiated at powerup, the self-calibra tion process requires the presence of a valid input clock. if self-calibration is init iated without a valid clock present, the device waits for a valid clock before completing self-calibration. the si5320 clock output is set to the lower end of the operating frequency range while the device is waiting for a valid clock. after the clock input is validated, the calibration process runs to completion; the device locks to the clock input, and the clock output shifts to its target frequency. subsequent losses of the input clock signal do not require re- calibration. if the clock inpu t is lost following self- 100 v dd 2.5 v 100 clkout? clkout+ 15 ma
si5320-xc3 rev. 2.7 25 calibration, the device enters digital hold mode. when the input clock retu rns, the device re-locks to the input clock without performing a self-calibration. during the calibration process, the output clock frequency is indeterminate and may jump as high as 5% above the final locked value. 3.11. bias generation circuitry the si5320 makes use of an external resistor to set internal bias currents. th e external resistor allows precise generation of bias currents, which significantly reduces power consumption and variation as compared to traditional implementations that use an internal resistor. the bias generation circuitry requires a 10 k (1%) resistor connected between rext and gnd. 3.12. differential input circuitry the si5320 provides a differential input for the clock input, clkin. this input is in ternally biased to a voltage of v icm (see table 2 on page 7) and may be driven by a differential or single-ended dr iver circuit. for differential transmission lines, the termination resistor is connected externally as shown. 3.13. differential output circuitry the si5320 utilizes a curr ent mode logic (cml) architecture to drive the differential clock output, clkout. for single-ended output operation, simply connect to either clkout+ or clkout? and leave the unused signal unconnected. 3.14. power supply connections the si5320 incorporates an on-chip voltage regulator. the voltage regulator requires an external compensation circuit of one resistor and one capacitor to ensure stability over all operating conditions. internally, the si5320 v dd33 pins are connected to the on-chip voltage regulator input, and the v dd33 pins also supply power to the device?s lvttl i/o circuitry. the v dd25 pins supply power to the core dspll circuitry and are also used for connection of the external compensation circuit. the regulator?s compensation circuit is actually a resistor and a capacitor in series between the v dd25 node and ground. (see "2. typical application schematic (3.3 v supply)" on page 17.) typically, the resistor is incorporated in to the capacitor?s equivalent series resistance (esr). the target rc time constant for this combination is 15 to 50 s. the capacitor used in the si5320 evaluation board is a 33 f tantalum capacitor with an esr of 0.8 . this gives an rc time constant of 26.4 s. the venkel part number, ta6r3tcr336kbr, is an example of a capacitor that meets these specs. to get optimal performance from the si5320 device, the power supply noise spectrum must comply with the plot in figure 11. this plot shows the power supply noise tolerance mask for the si5320. the customer should provide a 3.3 v supply that does not have noise density in excess of the amount shown in the diagram. however, the diagram cannot be used as spur criteria for a power supply that contains single tone noise. 3.15. design and layout guidelines precision clock circuits are susceptible to board noise and emi. to take precautions against unacceptable levels of board noise and emi affecting performance of the si5320, consider the following: ? power the device from 3.3 v since the internal regulator provides at least 40 db of isolation to the v dd25 pins (which power the pll circuitry). ? use an isolated local plane to connect the v dd25 pins. avoid running signal tr aces over or below this plane without a ground plane in between. ? route all i/o traces between ground planes as much as possible ? maintain an input clock amplitude in the 200 mv pp to 500 mv pp differential range. ? excessive high-frequency harmonics of the input clock should be minimized. the use of filters on the input clock signal can be used to remove high- frequency harmonics.
si5320-xc3 26 rev. 2.7 figure 11. power supply noise tolerance mask f v n ( v/ hz) 2100 42 10 khz 500 khz 100 mhz
si5320-xc3 rev. 2.7 27 4. pin descriptions: si5320 figure 12. si5320 pin configuration (bottom view) bottom view a b c d e f g h 1 7 8 65432 rstn/cal valtime frqsel[0] clkout+ clkout? frqsel[1] infrqsel[1] gnd gnd gnd gnd gnd gnd gnd infrqsel[0] gnd vdd25 vdd25 vdd25 vdd25 vdd25 los clkin? gnd vdd33 vdd33 vdd33 vdd25 vdd25 cal_actv clkin+ dblbw vdd33 vdd33 vdd33 vdd25 vdd25 dh_actv bwsel[1] vsel33 gnd gnd gnd gnd gnd bwsel[0] mode[1] fec[1] fec[0] t out [0] rsvd_nc rext infrqsel[2] t out [1] rsvd_nc rsvd_nc rsvd_nc mode[2] rsvd_nc fxddelay/ t in [0] decdelay/ t in [1] incdelay/ t in [2] mode[0]
si5320-xc3 28 rev. 2.7 figure 13. si5320 pin configuration (transparent top view) top view a b c d e f g h rstn/cal valtime frqsel[0] clkout+ clkout? frqsel[1] infrqsel[1]gndgndgndgndgndgndgnd infrqsel[0] gnd vdd25 vdd25 vdd25 vdd25 vdd25 los gnd vdd33 vdd33 vdd33 vdd25 vdd25 cal_actv clkin+ dblbw vdd33 vdd33 vdd33 vdd25 vdd25 dh_actv bwsel[1] vsel33 gnd gnd gnd gnd gnd mode[0] bwsel[0] rsvd_nc mode[2] mode[1] rsvd_nc fec[1] fec[0] rsvd_nc t out [1] rsvd_nc rsvd_nc rext infrqsel[2] clkin? 1 78 6 5 4 3 2 t out [0] incdelay/ t in [2] decdelay/ t in [1] fxddelay/ t in [0]
si5320-xc3 rev. 2.7 29 table 13. si5320 pin descriptions pin # pin name i/o signal level description d1 e1 clkin+ clkin? i see table 2 system clock input. clock input to the dspll ci rcuitry. the frequency of the clkin signal is multiplied by the dspll to gen- erate the clkout clock output. the input-to-output frequency multiplicat ion factor is set by selecting the clock input range and the clock output range. the frequency of the clkin clock input can be in the 19, 38, 77, 155, 311, or 622 mhz range (nominally 19.44, 38.88, 77.76, 155.52, 311.04, or 622.08 mhz) as indicated in table 3 on page 8. the clock input frequency is selected using the infrq- sel[2:0] pins. the clock output frequency is selected using the frqsel[1:0] pins. an additional scaling factor of either 255/238 or 238/255 may be selected for fec operation using the fec[1:0] con- trol pins. f1 g1 h1 infrqsel[0] infrqsel[1] infrqsel[2] i* lvttl input frequency range select. pins(infrqsel[2:0]) select the frequency range for the input clock, clkin. (see table 3 on page 8.) 000 = reserved. 001 = 19 mhz range. 010 = 38 mhz range. 011 = 77 mhz range. 100 = 155 mhz range. 101 = 311 mhz range. 110 = 622 mhz range. 111 = reserved. f8 los o lvttl loss-of-signal (los) alarm for clkin. active high output indicates that the si5320 has detected missing pulses on the input clock signal. the los alarm is cleared after either 100 ms or 13 seconds of a valid clkin clock input, depending on the setting of the valtime input. d8 dh_actv o lvttl digital hold mode active. active high output indicates that the dspll is in digital hold mode. digital hold mode locks the current state of the dspll and forces the dspll to continue generation of the output clock with no additional phase or frequency information from the input clock. *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 30 rev. 2.7 h3 rstn/cal i* lvttl reset/calibrate. when low, the internal circuitry enters the reset mode and all lvttl outputs are forced into a high- impedance state. also, the clkout+ and clkout? pins are forced to a nominal cml logic low and high respectively. this feature is useful for in-circuit te st applications. a low-to-high transition on rstn/cal initializes all digital logic to a known condition, enables the device output, and initiates self-calibration of the dspll. upon completion of self-calibration, the dspll begins to lock to the selected clock input signal. h6 h7 clkout+ clkout? ocml differential clock output. high frequency clock output. the frequency of the clkout output is a multiple of the frequency of the clkin input. the input-to-o utput frequency multipli- cation factor is set by selecting the clock input range and the clock output range . the frequency of the clkout clock output can be in the 19, 155, or 622 mhz range as indicated in table 3 on page 8. the clock output frequency is selected using the frqsel[1:0] pins. the clock input frequency is selected using the infrqsel[2:0] pins. an addi- tional scaling factor of either 255/238 or 238/255 may be selected for fec operation using the fec[1:0] control pins. h5 h8 frqsel[0] frqsel[1] i* lvttl clock output frequency range select select frequency range of the clock output, clk- out. (see table 3 on page 8.) 00 = clock driver powerdown. 01 = 19 mhz frequency range. 10 = 155 mhz frequency range. 11 = 622 mhz frequency range. table 13. si5320 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 rev. 2.7 31 a3 a2 fec[0] fec[1] i* lvttl forward error correction (fec) selection. enable or disable scaling of the input-to-output fre- quency multiplication factor for fec clock rate com- patibility. the frequency of the clkout output is a multiple of the frequency of the clkin input. the input-to-out- put frequency multip lication factor is set by selecting the clock input range and the clock output range. the clock output frequency is selected using the frqsel[1:0] pins. the clock input frequency is selected using the infrqsel[2:0] pins. an addi- tional scaling factor of either 255/238 or 238/255 may be selected for fec operation using the fec[1:0] control pins as indicated below. 00 = no fec scaling. 01 = 255/238 fec scaling for all clock outputs. 10 = 238/255 fec scaling for all clock inputs. 11 = reserved. note: fec[1:0] must be set to 00 when dblbw is set high. b1 c1 bwsel[0] bwsel[1] i* lvttl bandwidth select. bwsel[1:0] pins set the band width of the loop filter within the dspll to 6400, 3200, 1600, or 800 hz as indicated below. 00 = 3200 hz 01 = 1600 hz 10 = 800 hz 11 = 6400 hz note: the loop filter bandwidth will be twice the value indicated when dblbw is set high. e8 cal_actv o lvttl calibration mode active. this output is driven high during the dspll self-cal- ibration and the subsequent initial lock acquisition period. h4 valtime i* lvttl clock validation time for los. valtime sets the clock validation times for recovery from an los alarm condition. when valtime is high, the validation time is approximately 13 seconds. when valtime is low, the validation time is approximately 100 ms. b2, b3, b6, b7, c8 rsvd_gnd lvttl reserved?gnd. this pin must be tied to gnd for normal operation. table 13. si5320 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 32 rev. 2.7 a4?8, b5, b8 rsvd_nc lvttl reserved?no connect. this pin must be left unconnected for normal operation. c2 vsel33 i* lvttl select 3.3 v v dd supply. this is an enable pin for the internal regulator. to enable the regulator, connect this pin to the v dd33 pins. d3?d5, e3?e5 v dd33 v dd supply 3.3 v supply. 3.3 v power is applied to the v dd33 pins. typical supply bypassing/decoupling for this configuration is indicated in the typical application diagram for 3.3 v supply operation. d6, d7, e6, e7, f3?f7 v dd25 v dd supply 2.5 v supply. these pins provide a means of connecting the compensation network for the on-chip regulator. c3?c7, e2, f2, g2?g8 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of the device. h2 rext i analog external biasing resistor. used by on-chip circuitry to establish bias currents within the device. this pin must be connected to gnd through a 10 k (1%) resistor. d2 dblbw i* lvttl double bandwidth. active high input to boos t the selected bandwidth 2x. when this pin is high, the loop filter bandwidth selected on bwsel[1:0] is doubled. when this pin is high, fxddelay must also be high and fec[1:0] must be 00. b6 b7 c8 mode[2] mode[1] mode[0] ilvttl mode select. used to enable output phase adjust mode (output phase adjust register control). table 13. si5320 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 rev. 2.7 33 b4 fxddelay t in [0] t in [0] i* lvttl fixed delay mode. set high to disable hitless recovery from digital hold mode. this configuration is useful in applications that require a known or constant input-to-output phase relationship. when this pin is high, hitless switching from digital hold mode back to a valid clock input is disabled. when switching from digital hold mode to a valid clock input with fxddelay high, the clock output changes as necessary to re-establish the initial/ default input-to-output phas e relationship that is established after powerup or reset. the rate of change is determined by the setting of bwsel[1:0]. when this pin is low, hitless switching from digital hold mode back to a valid clock input is enabled. when switching from digital hold mode to a valid clock input with fxddelay low, the device enables "phase build out" to absorb the phase difference between the clock output and the clock input so that the phase change at the clock output is minimized. in this case, the input-to-output phase relationship following the transition out of digital hold mode is determined by the phase relationship at the time that switching occurs. note: fxddelay should remain at a static high or static low level during normal operation. transitions on this pin are allowed only when the rstn/cal pin is low. fxddelay must be set high when dblbw is set high. the state of fxdelay cannot be changed when the device is in the output phase adjust mode. instead, the device retains the last valid state of fxddelay and uses this setting for the duration of time the dev ice is in output phase adjust mode. envelope select (register read out). this pin must be held high to read the value of the phase detector dac (output phase adjust register control). serial clock input (output phase inc/dec). a rising edge on this pin drives serial data from t in [1] into the phase adjust registers (output phase adjust register control). table 13. si5320 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 34 rev. 2.7 b3 decdelay t in [1] ilvttl decrement output phase delay the incdelay and decdelay pins can adjust the phase of the si5320 clock output. adjustment is accomplished by driving a pulse (a transition from low to high and then back to low) into one of the pins while the other pin is he ld at a logic low level. each pulse on the decdelay pin removes a fixed delay from the si5320?s clock output. the fixed delay time is equal to twice the period of the 622 mhz output clock (t delay =2/f o_622 ). the frequency of the 622 mhz output clock (f o_622 ) is nominally 32x the frequency of the inpu t clock. the frequency of the 622 mhz output clock (fo_622) is scaled additionally according to the setting of the fec[1:0] pins. when the phase of the si5320 clock output is adjusted using the incdelay and/or decdelay pins, the output clock moves to its new phase set- ting at a rate of change that is determined by the setting of the bwsel[1:0] pins (output phase adjust pin control). serial data input (output phase inc/dec). input pin for transferring data into the phase adjust registers (output phase ad just register control). table 13. si5320 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 rev. 2.7 35 b2 incdelay/ t in [2] t in [2] ilvttl increment output phase delay. the incdelay and decdelay pins can adjust the phase of the si5320 clock output. adjustment is accomplished by driving a pulse (a transition from low to high and then back to low) into one of the pins while the other pin is he ld at a logic low level. each pulse on the incdelay pin adds a fixed delay to the si5320?s clock output. the fixed delay time is equal to twice the period of the 622 mhz output clock (t delay =2/f o_622 ). the frequency of the 622 mhz output clock (f o_622 ) is nominally 32x the frequency of the input clock. the frequency of the 622 mhz output clock (fo_622) is scaled additionally according to the setting of the fec[1:0] pins. when the phase of the si5320 clock output is adjusted using the incdelay and/or decdelay pins, the output clock moves to its new phase setting at a rate of change that is determined by the setting of the bwsel[1:0] pins (output phase adjust pin control) . incdelay is ignored when the si5320 is operating in digital hold (dh) mode. read register (register read out). this pin should be held high to shift the phase detector dac values out of the device (output phase adjust register control). load phase offset (output phase inc/dec). a rising edge on this signal loads data from the phase adjust registers into the phase offset circuitry (output phase adjust register control). a6 t out [0] o lvttl serial clock output (register read out). a rising edge on this pin shifts data from the device registers to the serial data output pin (t out [1]) (out- put phase adjust register control). a5 t out [1] o lvttl serial data output (register read out). output pin for transferring data out of the device registers (output phase ad just register control). table 13. si5320 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvtll inputs on the si5320 device have an internal pu lldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source.
si5320-xc3 36 rev. 2.7 5. ordering guide part number package temperature range si5320-g-xc3 63-ball cbga (prior revision) rohs-5 ?40 to 85 c SI5320-H-XL3 63-ball pbga (current revision) rohs-5 ?40 to 85 c si5320-h-zl3 63-ball pbga (current revision) rohs-6 ?40 to 85 c
si5320-xc3 rev. 2.7 37 6. package outline figure 14 illustrates the package details for the si5320-xc3. table 14 lists the valu es for the dime nsions shown in the illustration. figure 14. 63-ball plastic ball grid array (pbga) table 14. package diagram dimensions (mm) symbol min nom max symbol min nom max a 1.24 1.41 1.58 e1 7.00 bsc a1 0.40 0.50 0.60 e 1.00 bsc a2 0.34 0.38 0.42 s 0.50 bsc a3 0.50 0.53 0.56 aaa 0.10 b 0.50 0.60 0.70 bbb 0.10 d 9.00 bsc ccc 0.12 e 9.00 bsc ddd 0.15 d1 7.00 bsc eee 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-192, variation aab-1. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5320-xc3 38 rev. 2.7 7. 9x9 mm pbga card layout notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c spec ification for small body components. symbol min nom max x 0.40 0.45 0.50 c1 7.00 c2 7.00 e1 1.00 e2 1.00
si5320-xc3 rev. 2.7 39 d ocument c hange l ist revision 2.3 to revision 2.4 ? updated figure 5, ?output phase adjust timing diagrams (register control),? on page 6. ? added specification for register read out read clock high in table 3, ?ac characteristics,? on page 8. ? updated output phase increment/decrement example on page 22. ? updated "6. package outline" on page 37. revision 2.4 to revision 2.5 ? table 11 on page 21 updated. ? table 12 on page 22 updated. ? "3.7.2. output phase increment/decrement" on page 22 updated. revision 2.5 to revision 2.6 ? corrected pin assignments in table 11, ?output phase adjust control pins,? on page 21. revision 2.6 to revision 2.7 ? updated "5. ordering guide" on page 36. ? updated "6. package outline" on page 37. ? updated "7. 9x9 mm pbga card layout" on page 38.
si5320-xc3 40 rev. 2.7 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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